manuais Altera Arria V GZ Avalon-ST

Altera Arria V GZ Avalon-ST Manual do Utilizador (286 páginas)

Marca: Altera | Categoria: Instrumentos de medida | Tamanho: 2.31 MB |

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Índice

User Guide

1

Datasheet

2

Features

3

Interface

4

Release Information

7

Device Family Support

7

UG-01127_avst

10

2014.12.15

10

Debug Features

11

IP Core Verification

11

Recommended Speed Grades

12

• All Development Kits

14

PCI Express

15

Qsys Design Flow

16

Generating the Testbench

18

Simulating the Example Design

18

Directory Description

19

Time TLP Type Payload

19

TLP Header

19

Modifying the Example Design

23

Separate Component

24

Generating the Qsys System

27

Parameter Value

28

Parameter Settings

38

Parameter Value Description

39

Device Capabilities

45

Error Reporting

47

Link Capabilities

48

MSI and MSI-X Capabilities

49

Slot Capabilities

50

Power Management

51

PHY Characteristics

52

Avalon‑ST RX Interface

54

Packet TLP

59

Aligned Addresses

64

Single Packet Per Cycle

67

Avalon-ST TX Interface

70

Data 0 Header 2

83

Clock Signals

85

ECRC Forwarding

90

Error Signals

90

Interrupts for Endpoints

91

Completion Side Band Signals

92

Signal Directi

93

Description

93

Parity Signals

95

LMI Signals

96

Altera Corporation

100

Send Feedback

100

Field and Bit Map

105

0134678951

105

Bit(s) Field Description

106

Related Information

106

Signal Direction Description

107

Power Management Signals

108

15 011623 8 2791213142431

110

Transceiver Reconfiguration

111

Serial Data Signals

112

PIPE Interface Signals

116

Test Signals

121

Registers

122

Altera-Defined VSEC Registers

130

CvP Registers

131

2014.08.18

132

Bits Register Description

135

Reset and Clocks

138

Example Design

139

Hard IP for PCI Express

139

Clock Domains

142

Data Rate Frequency

143

Clock Summary

145

Interrupts

146

MSI Interrupts

147

Allocated

148

Implementing MSI-X Interrupts

149

Legacy Interrupts

151

Interrupts for Root Ports

152

Error Handling

153

Physical Layer Errors

154

Data Link Layer Errors

154

Transaction Layer Errors

155

Error Type Description

156

Status Bit Conditions

159

IP Core Architecture

161

Hard IP for PCI Express

162

Top-Level Interfaces

163

Avalon-ST Interface

163

Clocks and Reset

164

Hard IP Reconfiguration

164

Transaction Layer

165

Configuration Space

167

(Soft Logic)

168

Altera FPGA

168

Protocol Extensions Supported

172

Data Link Layer

172

Physical Layer

174

TX Packets

175

Supported Message Types

177

INTX Messages

177

Power Management Messages

178

Error Signaling Messages

179

Locked Transaction Message

180

Slot Power Limit Message

180

Vendor-Defined Messages

180

Hot Plug Messages

181

Receive Buffer Reordering

183

Using Relaxed Ordering

185

Throughput Optimization

188

Throughput of Posted Writes

190

Design Implementation

192

CONF_DONE

193

Endpoint Reset

193

Root Port Reset

193

SDC Timing Constraints

194

Optional Features

196

ECRC on the RX Path

197

ECRC on the TX Path

198

Subscribe

201

Testbench and Design Example

205

Root Port Testbench

208

Chaining DMA Design Examples

208

Root Complex

210

Chaining DMA

210

Hard IP for

210

BAR/Address Map

213

Memory BAR Mapping

214

Bit Field Description

215

Addr Register Name

215

Byte Address

218

Offset to Base

218

Descriptor Type Description

218

Bits[21:18] Bit[17] Bit[16]

219

Descriptor Field Endpoint

219

RC Access Description

219

Test Driver Module

220

DMA Write Cycles

221

Shared Memory

222

DMA Read Cycles

223

Registers (BAR2)

224

Root Port Design Example

225

Root Port

226

Variation

226

(variation_name.v)

226

Root Port BFM

227

BFM Configuration Procedures

228

BFM Request Interface

228

BFM Memory Map

229

Offset (Bytes) Description

231

BFM Procedures and Functions

235

Location altpcietb_bfm_rdwr.v

236

Express address

237

Shared Memory Constants

244

Constant Description

245

Location

250

Debugging Simulations

262

Debugging

263

Setting Up Simulation

269

Use Third-Party PCIe Analyzer

270

BIOS Enumeration Issues

270

Address[31:2]

271

Figure A-6: I/O Read Request

273

7 6 5 4 3 2 1 0

277

Core Config 8 4 1

277

Additional Information

279

Date Version Changes Made

280

How to Contact Altera

283

Typographic Conventions

284

Visual Cue Meaning

285

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