Altera Arria V GX Starter Board Manual do Utilizador descarregar pdf (Página 52)

2–44 Chapter 2: Board Components

Memory

Arria V GX Starter Board November 2013 Altera Corporation

Reference Manual

F11

FSM_D13

AJ26 2.5-V Data bus

G10

FSM_D14

AK27 2.5-V Data bus

G11

FSM_D15

AK26 2.5-V Data bus

FSM_D16

AL27 2.5-V Data bus

FSM_D17

AL28 2.5-V Data bus

FSM_D18

AL29 2.5-V Data bus

FSM_D19

AL31 2.5-V Data bus

FSM_D20

AM31 2.5-V Data bus

FSM_D21

AM29 2.5-V Data bus

FSM_D22

AM28 2.5-V Data bus

FSM_D23

AL26 2.5-V Data bus

FSM_D24

AL25 2.5-V Data bus

FSM_D25

AM26 2.5-V Data bus

FSM_D26

AM25 2.5-V Data bus

FSM_D27

AN26 2.5-V Data bus

FSM_D28

AP28 2.5-V Data bus

FSM_D29

AP27 2.5-V Data bus

FSM_D30

AP26 2.5-V Data bus

FSM_D31

AP25 2.5-V Data bus

SRAM_ADSCN

AP19 2.5-V Address status controller

SRAM_ADSPN

AF19 2.5-V Address status processor

SRAM_ADVN

AE19 2.5-V Address valid

SRAM_BWEN

AP17 2.5-V Byte write enable

SRAM_BWN0

AM17 2.5-V Byte lane 0 write enable

SRAM_BWN1

AM19 2.5-V Byte lane 1 write enable

SRAM_BWN2

AN17 2.5-V Byte lane 2 write enable

SRAM_BWN3

AN18 2.5-V Byte lane 3 write enable

SRAM_CEN

AL19 2.5-V Chip enable

SRAM_CLK

AL18 2.5-V Clock

N11

SRAM_DQP0

AF20 2.5-V Data bus parity byte lane 0

C11

SRAM_DQP1

AE20 2.5-V Data bus parity byte lane 1

SRAM_DQP2

AE22 2.5-V Data bus parity byte lane 2

SRAM_DQP3

AE21 2.5-V Data bus parity byte lane 3

SRAM_GWN

AF22 2.5-V Global write enable

SRAM_MODE

AG21 2.5-V Burst sequence selection

SRAM_OEN

AL17 2.5-V Output enable

H11

SRAM_ZZ

AD21 2.5-V Power sleep mode

Table 2–45. SSRAM Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2)

Board

Reference (U14)

Schematic

Signal Name

Arria V GX

Pin Number

I/O Standard Description

1 2 ... 47 48 49 50 51 52 53 54 55 56 57 ... 61 62

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