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Chapter 2: Board Components 2–7

MAX V CPLD 5M2210 System Controller

November 2013 Altera Corporation Arria V GX Starter Board

Reference Manual

MAX V CPLD 5M2210 System Controller

The board utilizes the 5M2210 System Controller, an Altera MAX V CPLD, for the

following purposes:

■ FPGA configuration from flash

■ Power measurement

■ Fan control (shared with the FPGA)

■ Control registers for clocks

■ Control and status registers for remote system update

Figure 2–4 illustrates the MAX V CPLD 5M2210 System Controller's functionality and

external circuit connections as a block diagram.

Table 2–5 lists the I/O signals present on the MAX V CPLD 5M2210 System

Controller. The signal names and functions are relative to the MAX V device (U15).

Figure 2–4. MAX V CPLD 5M2210 System Controller Block Diagram

Information

On-Board

USB-Blaster II

Si571

Controller

Si5538

Controller

SLD-HUB

PFL

FSM BUS

MAX V CPLD System Controller

Power

Measurement

Results

Virtual-JTAG

FPGA

LTC2418

Controller

Flash

Decoder

Encoder

GPIO

JTAG Control

Flash

SSRAM

Control

Si571

Programmable

Oscillator

Si5338

Programmable

Oscillator

Table 2–5. MAX V CPLD 5M2210 System Controller Device Pin-Out (Part 1 of 6)

Board

Reference (U15)

Schematic Signal Name I/O Standard Description

5M2210_JTAG_TMS

2.5-V MAX V JTAG TMS

CLK125_EN

2.5-V 125 MHz oscillator enable

CLK50_EN

2.5-V 50 MHz oscillator enable

CLK_CONFIG

2.5-V 100 MHz configuration clock input

A15

CLK_ENABLE

2.5-V DIP switch for clock oscillator enable

A13

CLK_SEL

2.5-V DIP switch for clock select—SMA or oscillator

J12

CLKIN_50_MAXV

2.5-V 50 MHz clock input

1 2 ... 10 11 12 13 14 15 16 17 18 19 20 ... 61 62

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