Altera Stratix GX Manual do Utilizador descarregar pdf (Página 12)

Application Note 147

AN147-12

an147f

Figure 12. PLL altpll_source4 Timing Diagram

The clock rx_inclk is delivered to the differential receiver

to generate a complex internal clock tree for the SERDES

circuitry—we don’t need to worry too much about that.

The clock pre_clk goes through a clock buffer (altclkctrl1),

which is controlled by circuit altbram_ctrl, to clock

altmem_ram2, which is built by FPGA block RAM, and

address generator altbram_addr. The clock othclk is cre

ated for other applications such as an LVDS receiver reset

generator,

bit-slip pulse generator, etc. The clock clldclk

drives a 16-bit parallel data bus output and generates the

signal cllctrl. The clock cllclk directly drives the output

clock pin for user-capture of the 16-bit parallel data.

As mentioned above, we have a controller built by a small

block BRAM accessible by the host from the JTAG interface

using Altera tools. Here is the register definition:

Address Offset: 0x00

Table 3. DPA Status Register

BIT 7 6 5 4 3 2 1 0

Bit Name CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

Read/Write Read

Initial Value 0x00

CHx: Channelx (0–7) serial line is locked by DPA.

1: locked 0: unlocked

1 2 ... 7 8 9 10 11 12 13 14 15 16 17 18

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Altera Stratix GX Manual do Utilizador Página 12