Altera Ethernet Blaster Communications Cable Especificações Página 175
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x16x8SidePackageMember Code
15Top
484-pin Micro FineLine BGA
D7
04Right
16Bottom
15Top
484-pin Ultra FineLine BGA 14Right
16Bottom
27Top
484-pin FineLine BGA 02Right
16Bottom
27Top
672-pin FineLine BGA 06Right
28Bottom
310Top
896-pin FineLine BGA 310Right
310Bottom
15Top
484-pin Ultra FineLine BGA
D9
04Right
16Bottom
15Top
484-pin FineLine BGA 02Right
16Bottom
27Top
672-pin FineLine BGA 06Right
28Bottom
310Top
896-pin FineLine BGA 310Right
310Bottom
412Top
1152-pin FineLine BGA 411Right
412Bottom
Related Information
Cyclone V Device Pin-Out Files
Download the relevant pin tables from this web page.
External Memory Interfaces in Cyclone V Devices
Altera Corporation
Send Feedback
CV-52006
DQ/DQS Groups in Cyclone V GT
6-10
2013.05.06
- Contents 2
- Related Information 10
- LAB Control Signals 13
- ALM Resources 14
- ALM Output 15
- ALM Operating Modes 16
- Normal Mode 17
- Extended LUT Mode 17
- Arithmetic Mode 17
- Shared Arithmetic Mode 18
- Types of Embedded Memory 21
- Total RAM Bit (Kb) 22
- MLABM10K 22
- Embedded Memory Features 27
- MLABM10KFeatures 28
- Embedded Memory Modes 30
- Single Clock Mode 32
- Read/Write Clock Mode 32
- Input/Output Clock Mode 32
- Independent Clock Mode 32
- Parity Bit in Memory Blocks 33
- Data Byte Output 34
- RAM Blocks Operations 34
- Features 38
- Resources 40
- Design Considerations 41
- Block Architecture 42
- Input Register Bank 43
- Pre-Adder 45
- Internal Coefficient 45
- Multipliers 45
- Systolic Registers 47
- Double Accumulation Register 47
- Output Register Bank 47
- Independent Multiplier Mode 48
- 18 x 19 Complex Multiplier 51
- Multiplier Adder Sum Mode 52
- Systolic FIR Mode 53
- 27-Bit Systolic FIR Mode 54
- Initial release.1.0May 2011 56
- Clock Networks 57
- Source of Clock Resource 58
- Number of Resources 58
- Available 58
- DeviceClock Resource 58
- Global Clock Networks 59
- Regional Clock Networks 60
- Clock Sources Per Quadrant 61
- Types of Clock Regions 62
- Clock Network Sources 63
- PLL Clock Outputs 64
- Clock Output Connections 65
- Clock Control Block 65
- GCLK Control Block 66
- RCLK Control Block 66
- PCLK Control Block 67
- Clock Power Down 68
- Clock Enable Signals 68
- Cyclone V PLLs 70
- PLL Strip 72
- Fractional PLL Architecture 74
- Fractional PLL Usage 75
- PLL Control Signals 76
- Clock Feedback Modes 77
- Source Synchronous Mode 78
- Direct Compensation Mode 79
- Zero-Delay Buffer Mode 80
- External Feedback Mode 81
- Automatic Switchover 84
- Manual Clock Switchover 87
- Guidelines 88
- Standard SupportI/O Standard 95
- Altera Corporation 100
- Send Feedback 100
- PLLs and Clocking 102
- Guideline: Use the Same V 107
- Voltage in the Same Bank 108
- HPS Core 110
- A4A2Member Code 111
- C5C4C3Member Code 112
- A9A7A5Member Code 112
- C9C7Member Code 113
- D7D5Member Code 113
- D9Member Code 114
- F1152F896F672F484U484Package 114
- A6A5A4A2Member Code 114
- C6C5C4C2Member Code 115
- D6D5Member Code 116
- F896F896Package 116
- Output PathInput Path 117
- Programmable Current Strength 119
- Programmable IOE Delay 120
- Programmable Pre-Emphasis 121
- Open-Drain Output 122
- Bus-Hold Circuitry 123
- Pull-up Resistor 123
- Uncalibrated OCT (Output) 124
- I/O Standard 124
- CV-52005 125
- 2013.06.21 125
- Calibrated OCT (Output) 126
- Calibrated OCT (Input) 128
- RZQ (Ω)R 128
- LVDS Input R 130
- OCT in Cyclone V Devices 130
- Calibration block 131
- Single-ended I/O Termination 134
- Differential I/O Termination 136
- LVPECL Termination 140
- GT D5, D7, and D9 Devices 142
- LVDS SERDES Circuitry 143
- RXTXSidePackageMember Code 145
- Transmitter Blocks 152
- Transmitter Clocking 153
- Deserializer 156
- LVDS Receiver Mode 156
- Differential Data Orientation 158
- Differential I/O Bit Position 159
- Internal 8-Bit Parallel Data 160
- Receiver Channel Data Number 160
- LSB PositionMSB Position 160
- Document Revision History 162
- ChangesVersionDate 163
- External Memory Performance 167
- Guideline: Using DQ/DQS Pins 168
- DQ/DQS Groups in Cyclone V E 169
- DQ/DQS Groups in Cyclone V GX 171
- DQ/DQS Groups in Cyclone V GT 174
- DQ/DQS Groups in Cyclone V SX 176
- DQ/DQS Groups in Cyclone V ST 176
- UniPHY IP 177
- DQS Phase-Shift Circuitry 178
- DQS Logic 180
- D9) Devices 181
- Delay-Locked Loop 182
- DLL Phase-Shift 184
- PHY Clock (PHYCLK) Networks 185
- DQS Logic Block 187
- Update Enable Circuitry 188
- DQS Delay Chain 188
- DQS Postamble Circuitry 188
- Dynamic OCT Control 189
- IOE Registers 190
- Output Registers 191
- Delay Chains 192
- Hard Memory Controller 194
- DescriptionFeature 195
- Multi-Port Front End 196
- Bonding Support 197
- Member Code 199
- Package A9A7A5A4A2 199
- MSEL Pin Settings 205
- Configuration Sequence 206
- Power Up 207
- Configuration 208
- Configuration Error Handling 208
- Device Configuration Pins 209
- Configuration Pin 210
- Using One Configuration Data 214
- Active Serial Configuration 214
- Using EPCS and EPCQ Devices 218
- Passive Serial Configuration 222
- JTAG Configuration 226
- CONFIG_IO JTAG Instruction 229
- Remote System Upgrades 231
- Configuration Images 232
- DescriptionRegister 234
- Control Register 235
- Status Register 235
- Design Security 236
- ALTCHIP_ID Megafunction 237
- JTAG Secure Mode 237
- Security Key Types 238
- Security Modes 238
- Error Detection Features 241
- Configuration Error Detection 241
- User Mode Error Detection 241
- Specifications 242
- Error Detection Frequency = 243
- Internal Oscillator Frequency 243
- Enabling Error Detection 244
- CRC_ERROR Pin 245
- Error Detection Registers 245
- Double Word 246
- Location 246
- Error Detection Process 247
- BST Operation Control 250
- Supported JTAG Instruction 252
- JTAG Private Instruction 255
- Performing BST 256
- Power Consumption 261
- Hot-Socketing Feature 262
- Hot-Socketing Implementation 262
- Power-Up Sequence 263
- Current Transient (mA) 264
- Power Rail 264
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