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Chapter 7: Functional Description—High-Performance Controller II 7–19
Register Maps Description
December 2010 Altera Corporation External Memory Interface Handbook Volume 3
Section II. DDR3 SDRAM Controller with ALTMEMPHY IP User Guide
ALTMEMPHY Register Map
The ALTMEMPHY register map allows you to control the memory components’
mode register settings. To access the ALTMEMPHY register map, connect the
ALTMEMPHY Debug interface signals in Table 7–8 using the Avalon-MM protocol.
After configuring the ALTMEMPHY register map, initialize a calibration request by
setting bit 2 in the CSR register map address 0x100 (Table 7–12) for the mode register
settings to take effect.
1 DDR3 SDRAM with leveling does not support the ALTMEMPHY register map. For
more information about DDR3 SDRAM with leveling, refer to “DDR3 SDRAM With
Leveling” on page 5–7.
Table 7–10. Address 0x005 Mode Register 0-1 (Part 1 of 2)
Bit Name Default Access Description
2:0 Burst length 8 RO
This value is set to 8 because the DDR3 SDRAM
HPC II only supports a burst length of 8.
3BT 0 RO
This value is set to 0 because DDR3 SDRAM
SDRAM HPC II only supports sequential bursts.
6:4 CAS latency — RW
CAS latency setting. The default value for these bits
is set by the MegaWizard CAS Latency setting for
your controller instance. You must set this value in
the CSR interface register map 0x126 (Table 7–20)
as well.
7 Reserved 0 — Reserved for future use.
8 DLL 0 RW
Not used by the controller, but you can set and
programm into the memory device mode register.
11:9 Write recovery — RW
Write recovery (t
WR
) setting. The default value for
these bits is set by the MegaWizard Write Recovery
(t
WR
) setting for your controller instance. You must
set this value in CSR interface register map 0x126
(Table 7–20) as well.
12 PD 0/1 RO
This value is set to 0 because DDR3 SDRAM HPC II
only supports power-down fast exit mode.
15:13 Reserved 0 — Reserved for future use.
16 DLL 0 RW
Not used by the controller, but you can set and
program into the memory device mode register.
17 ODS 0 RW
18 RTT 0 RW
21:19 AL — RW
Additive latency setting. The default value for these
bits is set by the MegaWizard Additive Latency
setting for your controller instance. You must set
this value in CSR interface register map 0x126
(Table 7–20) as well.
- User Guide 1
- Contents 3
- Chapter 8. Latency 5
- Chapter 9. Timing Diagrams 5
- 1. About This IP 7
- Release Information 8
- Device Family Support 8
- 1–4 Chapter 1: About This IP 10
- Features 10
- ALTMEMPHY Megafunction 11
- Note to Table 1–4: 12
- Note to Table 1–5: 12
- High-Performance Controller 13
- System Requirements 14
- Installation and Licensing 14
- Free Evaluation 15
- 1–10 Chapter 1: About This IP 16
- 2. Getting Started 17
- Specifying Parameters 18
- SOPC Builder Flow 19
- Generated Files 22
- 3. Parameter Settings 29
- Memory Settings 30
- ALTMEMPHY Parameter Settings 31
- Note to Table 3–3: 34
- Note to Table 3–5: 38
- PHY Settings 39
- Board Settings 41
- Controller Settings 42
- 4. Compiling and Simulating 47
- Compiling the Design 48
- Simulating the Design 50
- Calibration 55
- DDR3 SDRAM Without Leveling 55
- Step 6: Postamble 57
- Step 7: Prepare for User Mode 57
- DDR3 SDRAM With Leveling 59
- Step 2: Write Leveling 62
- Address and Command Datapath 63
- ° ), or the inverted 64
- Clock and Reset Management 65
- Clock Management 65
- Note to Table 5–1: 67
- Reset Management 69
- Read Datapath 70
- Write Datapath 74
- ALTMEMPHY Signals 75
- Notes to Table 5–3: 77
- Note to Table 5–3: 79
- Notes to Table 5–5: 82
- PHY-to-Controller Interfaces 83
- Notes to Figure 5–17: 86
- Notes to Figure 5–18: 87
- Notes to Figure 5–19: 88
- Notes to Figure 5–20: 89
- Preliminary Steps 90
- Design Considerations 90
- Clocks and Resets 90
- Using a Custom Controller 91
- 6. Functional Description— 95
- Command FIFO Buffer 96
- PHY Interface Logic 98
- Control Logic 99
- Figure 6–3. ECC Block Diagram 100
- Block Description 101
- Interrupts 102
- Partial Writes 102
- Partial Bursts 103
- ECC Latency 103
- ECC Registers 104
- ECC Register Bits 106
- Example Top-Level File 108
- Example Driver 109
- Top-level Signals Description 110
- or vhd file 111
- Note to Table 6–14: 114
- 7. Functional Description— 117
- Write Data FIFO Buffer 120
- Command Queue 120
- Bank Management Logic 120
- Timer Logic 121
- Command-Issuing State Machine 121
- ODT Generation Logic 122
- User-Refresh Commands 122
- Multi-Cast Write 122
- Low-Power Mode Logic 123
- Error Correction Coding (ECC) 123
- Notes to Table 7–7: 133
- Register Maps Description 134
- ALTMEMPHY Register Map 135
- Controller Register Map 137
- 8. Latency 143
- 8–2 Chapter 8: Latency 144
- Chapter 8: Latency 8–3 145
- 8–4 Chapter 8: Latency 146
- 9. Timing Diagrams 147
- Auto-Precharge 148
- [1] [2] [3] 148
- User Refresh 149
- Initialization Timing 156
- Calibration Timing 158
- AABBCCDD AABBCCDD AABBCCDD 162
- EEFF0011 EEFF0011 EEFF0011 162
- [1] [3] [4][2] 166
- Half-Rate Read With Gaps 168
- Half-Rate Write With Gaps 169
- [2][1] [5] [4] [6][3] 170
- [12][6][7][10] [11] 172
- Additional Information 175
- Typographic Conventions 176
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