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Altera Transceiver Signal Integrity Development Kit, Stra Manual do Utilizador Página 24

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2–16 Chapter 2: Board Components
Configuration, Status, and Setup Elements
Transceiver Signal Integrity Development Kit May 2014 Altera Corporation
Stratix V GT Edition Reference Manual
Figure 2–4 shows the MAX II and flash FPP configuration.
f For more information on the flash memory map storage, refer to the Transceiver Signal
Integrity Development Kit, Stratix V GT Edition User Guide.
Flash Programming
Flash programming is possible through a variety of methods using the Stratix V GT
device.
The first method is to use the factory design called the Board Update Portal. This
design is an embedded webserver, which serves the Board Update Portal web page.
The web page allows you to select new FPGA designs including hardware, software,
or both in an industry-standard S-Record File (.flash) and write the design to the user
hardware page (page 1) of the flash over the network.
The secondary method is to use the pre-built PFL design included in the development
kit. The development board implements the Altera PFL megafunction for flash
programming. The PFL megafunction is a block of logic that is programmed into an
Altera programmable logic device (FPGA or CPLD). The PFL functions as a utility for
writing to a compatible flash device. This pre-built design contains the PFL
megafunction that allows you to write either page 0, page 1, or other areas of flash
over the USB interface using the Quartus II software. This method is used to restore
the development board to its factory default settings.
Other methods to program the flash can be used as well, including the Nios
®
II
processor.
Figure 2–4. MAX II and Flash FPP Configuration
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