Altera Transceiver Signal Integrity Development Kit, Stra Manual do Utilizador descarregar pdf (Página 13)

Chapter 2: Board Components 2–3

Board Overview

November 2011 Altera Corporation Transceiver Signal Integrity Development Kit,

Stratix IV GT Edition Reference Manual

U32 MAX II CPLD

Altera EPM1270256C3N, MAX II 256-pin CPLD for MAX II+FPP

configuration.

D6 Fan LED

Indicates an FPGA over-temperature condition exists and a fan should

be attached to the FPGA and running.

D16–D18 Configuration status LEDs LEDs to indicate the status of FPP configuration.

J62

Configuration program select

jumper

Jumper to select the flash configuration image to load upon power-on

or reset.

J65 Y3 OSC enable/disable jumper Jumper to enable or disable the Y3 OSC.

J66 Y4 OSC enable/disable jumper Jumper to enable or disable the Y4 OSC.

J67 Y5 OSC enable/disable jumper Jumper to enable or disable the Y5 OSC.

D3 Power LED Blue LED to indicate board power status.

D7 USB-Blaster LED Green activity status LED for the embedded USB-Blaster.

D19–D24

Bank of Ethernet LINK and

Status LEDs

Ethernet Link, Speed, Full Duplex, Transmit and Receive activity LEDs.

SW16

Power measurement rotary

switch

This switch selects 1 of 6 measured FPGA power rails to display on the

LCD.

SW2

Spread spectrum

configuration DIP switch

DIP switch to set the spread spectrum output clock frequency and

down-spread percentages.

J18 Spread spectrum clock trigger Spread spectrum clock source routed to SMA for triggering purposes.

J21 Y3 OSC clock trigger Y3 oscillator clock source routed to SMA for triggering purposes.

J22 Y4 OSC clock trigger Y4 oscillator clock source routed to SMA for triggering purposes.

J23 Y5 OSC clock trigger Y5 oscillator clock source routed to SMA for triggering purposes.

J14, J15

Differential SMA clock input to

FPGA core

SMA for receiving a differential external clock input to the FPGA core.

J19, J20

Differential SMA clock input to

FPGA transceiver

SMA for receiving a differential external clock input to the FPGA

transceiver.

J16, J17

Differential SMA clock output

from FPGA core

SMA for sending a differential clock output from the FPGA core.

Clock Circuitry

Y2, U20 50-MHz OSC and clock buffer 50-MHz clock to the FPGA and MAX II CPLD.

Y3, U22

644.53-MHz OSC and clock

buffer

644.53-MHz clock to the FPGA transceivers.

Y4, U23

100-MHz OSC and clock

buffer

100-MHz clock to the FPGA transceivers.

Y5, U24

706.25-MHz OSC and clock

buffer

706.25-MHz clock to the FPGA transceivers.

X1 6-MHz XTAL XTAL for FTDI USB PHY device.

Y1 24-MHz OSC 24-MHz oscillator for embedded USB-Blaster MAX II CPLD.

X3 25-MHz OSC 25-MHz oscillator for Marvell 88E1111 Ethernet PHY device.

X2, U21

25-MHz OSC and spread

spectrum clock buffer

25-MHz oscillator and spread spectrum clock buffer circuitry.

Table 2–1. Stratix IV GT Transceiver Signal Integrity Development Board Components (Part 2 of 4)

Board Reference Type Description

1 2 ... 8 9 10 11 12 13 14 15 16 17 18 ... 41 42

Comentários a estes Manuais

Sem comentários

Altera Transceiver Signal Integrity Development Kit, Stra Manual do Utilizador Página 13

Comentários a estes Manuais

Manuais e produtos relacionados com Instrumentos de medida Altera Transceiver Signal Integrity Development Kit, Stra