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Chapter 6: Board Test System 6–5

Using the Board Test System

June 2011 Altera Corporation Stratix IV E FPGA Development Kit User Guide

The Config Tab

The Config tab shows information about the board’s current configuration.

Figure 6–1 on page 6–2 shows the Config tab. The tab displays the contents of the

MAX II registers, the JTAG chain, the board’s MAC address, the flash memory map,

and other details stored on the board.

The following sections describe the controls on the Config tab.

Board Information

The Board information controls display static information about your board.

■ MAX II ver—Indicates the version of MAX II code currently running on the board.

The MAX II code resides in the <install

dir>\kits\stratixIVE_4se530_fpga\examples directory. Newer revisions of this

code might be available on the Stratix IV E FPGA Development Kit page of the

Altera website.

■ MAC—Indicates the MAC address of the board.

MAX II Registers

The MAX II registers control allow you to view and change the current MAX II

take effect immediately. For example, writing a 0 to SRST resets the board.

■ PSO—Sets the MAX II PSO register. The following options are available:

■ Use PSR—Allows the PSR to determine the page of flash memory to use for

FPGA reconfiguration.

■ Use PSS—Allows the PSS to determine the page of flash memory to use for

FPGA reconfiguration.

■ PSR—Sets the MAX II PSR register. The numerical values in the list corresponds to

the page of flash memory to load during FPGA reconfiguration. Refer to Table 6–1

for more information.

■ PSS—Displays the MAX II PSS register value. Refer to Table 6–1 for the list of

available options.

Table 6–1. MAX II Registers

Read/Write

Capability

Description

System Reset

(SRST)

Write only Set to 0 to initiate an FPGA reconfiguration.

Page Select Register

(PSR)

Read / Write

Determines which of the up to eight (0-7) pages of flash

memory to use for FPGA reconfiguration. The flash memory

ships with pages 0 and 1 preconfigured.

Page Select Override

(PSO)

Read / Write

When set to 0, the value in PSR determines the page of

flash memory to use for FPGA reconfiguration. When set to

1, the value in PSS determines the page of flash memory to

use for FPGA reconfiguration.

Page Select Switch

(PSS)

Read only Holds the current value of the rotary switch (SW5).

1 2 ... 26 27 28 29 30 31 32 33 34 35 36 ... 57 58

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