Altera SerialLite II IP Core Manual do Utilizador Página 77
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Chapter 4: Functional Description 4–23
Signals
January 2014 Altera Corporation SerialLite II MegaCore Function
User Guide
Table 4–6 shows the transceiver megafunction signals.
f For more information on Altera gigabit transceiver (ALTGX
)
megafunction, refer to
the Arria II GX Transceiver Architecture section in volume 2 of the Arria II GX Device
Handbook, and the Stratix IV Transceiver Architecture section in volume 2 of the
Stratix IV Device Handbook.
mreset_n
Input Asynchronous
Master reset pin, active low. Asserting this signal
causes the entire SerialLite II MegaCore function,
including the Atlantic FIFO buffers, to be reset.
For Arria V, Cyclone V, and Stratix V designs, hold this
signal asserted until the Custom PHY asserts the
tx_ready
and
rx_ready
output ports.
ctrl_tc_force_train
Input
tx_coreclock
Force training patterns to be sent. Negate once the
receiver has locked. Only used in self-synchronizing
mode. Otherwise, this signal is currently reserved (tie
this signal to
1'b0
).
stat_tc_pll_locked
Output
tx_coreclock
PLL locked signal. Indicates that the ALTGX PLL has
locked to the
trefclk
.
stat_rr_link
(3)
Output
rrefclk
Link Status. When high, the link is enabled.
Notes to Table 4–5:
(1) n = RX number of lanes
(2) m = TX Number of lanes
(3) In broadcast mode, these signals will have the corresponding receiver function number post-fixed. For example,
err_rr_crc0
is the CRC error
signal from SerialLite II receiver block 0.
(4) This signal is removed in configurations targeted for Arria V, Cyclone V, and Stratix V devices due to the exclusion of hard transceivers.
Table 4–5. High-Speed Serial Interface Signals (Part 2 of 2)
Signal Direction Clock Domain Description
Table 4–6. Transceiver Megafunction Signals (Part 1 of 3)
Signal
(1)
,
(2)
Direction Clock Domain Description
ctrl_tc_serial_lpbena
(5)
Input
tx_coreclock
Serial Loopback (
TXOUT
internally connected to
RXIN
). Tie signal to
1'b0
to NOT use loopback, tie
to
1'b1
to Use Serial Loopback.
rcvd_clk_out
[rxnl-
1:0
]
Output Per lane recovered clock.
err_rr_8berrdet
(5)
[srx-
1:0
]
Output
rrefclk
8B/10B error detection signal.
err_rr_disp
[srx-
1:0
]
Output
rrefclk
Disparity error detection signal
err_rr_pcfifo_uflw
(5)
[rxnl-
1:0
]
Output
rrefclk
Interface/phase compensation FIFO buffer
underflow signal (Arria II GX and Stratix IV devices
only).
err_rr_pcfifo_oflw
(5)
[rxnl-
1:0
]
Output
rrefclk
Interface/phase compensation FIFO buffer overflow
signal (Arria II GX and Stratix IV devices only).
err_rr_rlv
[rxnl-
1:0
]
Output
rrefclk
Run length violation status signal.
- User Guide 1
- Contents 3
- Chapter 5. Testbench 5
- Release Information 6
- Device Family Support 6
- Features 7
- General Description 8
- (EP2GX90FF1508C3) 10
- Notes to Table 1–3: 11
- Installation and Licensing 13
- OpenCore Plus Evaluation 14
- Simulate with Testbench 16
- Design Flow 17
- Parameterize 18
- Set Up Simulation 21
- Generate Files 21
- Simulate the Design 22
- Instantiate the MegaCore 22
- Specify Constraints 22
- Compile and Program 23
- 3. Parameter Settings 24
- Link Consistency 25
- Physical Layer Configuration 25
- Transfer size 26
- Reference Clock Frequency 26
- Port Type 27
- Notes to Figure 3–3: 28
- Note to Figure 3–4: 28
- Note to Figure 3–5: 29
- Notes to Figure 3–6: 29
- Self Synchronized Link Up 30
- Number of Lanes 31
- Scramble 32
- De-Scramble 32
- Broadcast Mode 32
- Clock Compensation 33
- Link Layer Configuration 34
- Retry-on-error Disabled 35
- Retry-on-error Enabled 35
- Segment Size 35
- Retry-on-error 36
- Retry-on-error Responses 37
- Flow Control 38
- Notes to Figure 3–12: 41
- Notes to Table 3–6: 42
- Transmit/Receive FIFO Buffers 43
- FIFO Buffer Size 44
- FIFO Buffer Structure 44
- 16-Bit Versus 32-Bit CRC 46
- Transceiver Configuration 47
- Transmitter Buffer Power (V 48
- Equalizer Control Settings 48
- Bandwidth Mode 48
- Starting Channel number 49
- ALTGX Support Signals 50
- Error Handling 51
- Optimizing the Implementation 52
- Feature Selection 53
- Running Different Seeds 53
- Limiting Fanout 53
- Floorplanning 53
- Minimizing Memory Utilization 54
- 4. Functional Description 55
- Atlantic Interface 56
- High-Speed Serial Interface 57
- Clocks and Data Rates 58
- External Clock Modes 59
- SerialLite II Deskew Support 60
- Note to Figure 4–6: 61
- Note to Figure 4–7: 62
- Note to Figure 4–8: 63
- Note to Figure 4–9: 64
- Note to Figure 4–10: 65
- Note to Figure 4–11: 66
- Note to Figure 4–14: 69
- Initialization and Restart 71
- Multiple Core Configuration 72
- Compilation 73
- Testbench 74
- Simulation Support 74
- Notes to Table 4–5: 77
- Notes to Table 4–6: 79
- Notes to Table 4–7: 81
- Notes to Table 4–8: 81
- Notes to Table 4–9: 82
- Note to Table 4–10: 84
- MegaCore Verification 85
- 5. Testbench 87
- Testbench Specifications 88
- Notes to Figure 5–1: 89
- 5–4 Chapter 5: Testbench 90
- Simulation Flow 91
- Running a Simulation 92
- Chapter 5: Testbench 5–7 93
- Testbench Time-Out 94
- Verilog HDL 95
- 5–10 Chapter 5: Testbench 96
- Chapter 5: Testbench 5–11 97
- Chapter 5: Testbench 5–13 99
- 5–14 Chapter 5: Testbench 100
- Status Monitors (pin_mon) 101
- Pin_mon Tasks - Verilog HDL 102
- Chapter 5: Testbench 5–17 103
- 5–18 Chapter 5: Testbench 104
- Chapter 5: Testbench 5–19 105
- 5–20 Chapter 5: Testbench 106
- Chapter 5: Testbench 5–21 107
- Additional Information 108
- Typographic Conventions 109
- Visual Cue Meaning 110
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