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Nios Development Board Reference Manual, Stratix II Edition July 2005
Component List
Table 2–1. Nios Development Board, Stratix Edition Components & Interfaces (Part 1 of 2)
Board Designation Name Description
Featured Device
U60 Stratix II FPGA EP2S60F672C5 or EP2S30F672C5 device with mounted
heat sink
User Interface
SW0 – SW3 Push-button
switches
Four momentary contact switches for user input to the FPGA
D0 – D7 Individual LEDs Eight individual LEDs driven by the FPGA
U8, U9 Seven-segment
LEDs
Two seven-segment LEDs to display numeric output from the
FPGA
Memory
U35, U36 SRAM memory Two SRAM chips combined to form 1 Mbyte of fast, static
RAM
U5 Flash memory 16 Mbytes of nonvolatile memory for use by both the FPGA
and the configuration controller
U57 SDRAM memory 16 Mbytes of SDRAM
Connectors & Interfaces
U4, RJ1 Ethernet
MAC/PHY
10/100 Ethernet MAC/PHY chip connected to an RJ-45
Ethernet connector
J19, J27 Serial connectors Two serial connectors with 5 V-tolerant buffers. Supports all
RS-232 signals.
PROTO1 (J11, J12, J13) Expansion
prototype
connector
Expansion headers connecting to 41 I/O pins on the FPGA.
Supplies 3.3V and 5.0V for use by a daughter card.
PROTO2 (J15, J16, J17) Expansion
prototype
connector
Expansion headers connecting to 41 I/O pins on the FPGA.
Supplies 3.3V and 5.0V for use by a daughter card.
CON3 CompactFlash
connector
CompactFlash connector for memory expansion
J25 Mictor connector Mictor connector for debugging Nios II systems using a First
Silicon Solutions (FS2) debug probe.
J24 JTAG connector Connects to the FPGA allowing hardware configuration from
Quartus II software and software debug from the Nios II IDE.
J5 JTAG connector Connects to the configuration controller
Configuration & Reset
U3 Configuration
controller
Altera EPM7128AE device used to configure the FPGA from
flash memory
- Nios Development Board 1
- MNL-N832T4-1.2 2
- Contents 3
- Shared Bus Table 1 4
- About this Manual 5
- How to Contact 6
- Typographic 7
- Conventions 7
- July 2005 8
- Typographic Conventions 8
- Introduction 9
- 1–2 Altera Corporation 10
- General Description 10
- Factory 11
- Programmed 11
- Reference 11
- 1–4 Altera Corporation 12
- Board Components 13
- Stratix II Device 15
- Push-Button 17
- Switches (SW0 17
- Individual LEDs 17
- (D0 - D7) 17
- Seven-Segment 18
- LEDs (U8 & U9) 18
- SRAM Memory 18
- (U35 & U36) 18
- Flash Memory 19
- SDRAM Memory 20
- Ethernet 22
- MAC/PHY (U4) 22
- Serial Port 22
- Connectors (J19 22
- & J27) 22
- Expansion 23
- Prototype 23
- Connectors 23
- (PROTO1 & 23
- Altera Corporation 2–17 25
- Note to Figure 2–8 25
- 2–18 Altera Corporation 26
- Altera Corporation 2–19 27
- Notes to Figure 2–10 27
- CompactFlash 28
- Connector 28
- Connector (J25) 31
- 2–24 Altera Corporation 32
- Mictor Connector (J25) 32
- Configuration 33
- Controller 33
- Device (U3) 33
- Factory & User 34
- Configurations 34
- Flash Memory Partitions 35
- User Configuration 36
- Factory Configuration 36
- Persistent Data 36
- Configuration-Status LEDs 37
- SW8 – CPU Reset 38
- SW9 – Factory Config 38
- SW10 – Reset, Config 38
- Connectors (J24 39
- & J5) 39
- 2–32 Altera Corporation 40
- ° compared to J24 41
- Clock Circuitry 42
- Power-Supply 43
- Circuitry 43
- 2–36 Altera Corporation 44
- Power-Supply Circuitry 44
- Appendix A. Shared Bus Table 45
- Shared Data 46
- WE_n.ACC 47
- A–4 Altera Corporation 48
- July 2005 48
- Description 48
- Appendix B. Restoring the 49
- B–2 Altera Corporation 50
- Appendix C. Connecting to the 51
- Board via Ethernet 51
- Connecting the 52
- LCD Screen 52
- Obtaining an IP 52
- LAN Connection 53
- Point–to–Point Connections 54
- Browsing to Your 55
- C–6 Altera Corporation 56
- Browsing to Your Board 56
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