Altera Mentor Verification IP Altera Edition AMBA AXI4-St Manual do Utilizador Página 156
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Mentor Verification IP AE AMBA AXI4-Stream User Guide, V10.3
156
VHDL Slave BFM
wait_on()
April 2014
wait_on()
This blocking procedure waits for an event on the ACLK or ARESETn signals to occur before
proceeding. An optional count argument waits for the number of events equal to count.
Example
wait_on(AXI4STREAM_RESET_POSEDGE, bfm_index,
axi4stream_tr_if_0(bfm_index));
wait_on(AXI4STREAM_CLOCK_POSEDGE, 10, bfm_index,
axi4stream_tr_if_0(bfm_index));
Prototype
procedure wait_on
(
phase : in integer;
count: in integer; -optional
bfm_id : in integer;
signal tr_if : inout axi4stream_vhd_if_struct_t
);
Arguments
phase Wait for:
AXI4STREAM_CLOCK_POSEDGE
AXI4STREAM_CLOCK_NEGEDGE
AXI4STREAM_CLOCK_ANYEDGE
AXI4STREAM_CLOCK_0_TO_1
AXI4STREAM_CLOCK_1_TO_0
AXI4STREAM_RESET_POSEDGE
AXI4STREAM_RESET_NEGEDGE
AXI4STREAM_RESET_ANYEDGE
AXI4STREAM_RESET_0_TO_1
AXI4STREAM_RESET_1_TO_0
count (Optional) Wait for a number of events to occur set by
count.
bfm_id BFM identifier. Refer to “Overloaded Procedure
Common Arguments” on page 87 for more details.
tr_if Transaction signal interface. Refer to
for more details.
Returns
None
- AMBA AXI4-Stream User Guide 1
- Table of Contents 3
- List of Examples 10
- List of Figures 11
- List of Tables 12
- About This User Guide 13
- Supported Simulators 13
- Simulator GCC Requirements 14
- Chapter 1 17
- Mentor VIP Altera Edition 17
- What Is a Transaction? 18
- AXI4-Stream Transactions 19
- Chapter 2 21
- SystemVerilog API Overview 21
- Configuration 22
- Creating Transactions 22
- Transaction Record 23
- Executing Transactions 26
- Waiting Events 27
- Access Transaction Record 27
- Operation Mode 28
- Handshake Delay 29
- Transfer Done 30
- Transaction Done 30
- Chapter 3 31
- SystemVerilog Master BFM 31
- Master BFM Configuration 32
- Master Assertions 34
- SystemVerilog Master API 35
- Returns 36
- Arguments config_name 37
- Chapter 4 43
- SystemVerilog Slave BFM 43
- SystemVerilog Slave API 47
- Chapter 5 55
- SystemVerilog Monitor BFM 55
- SystemVerilog Monitor API 59
- Chapter 6 67
- SystemVerilog Tutorials 67
- Chapter 7 75
- VHDL API Overview 75
- Test Program VHDL 76
- Chapter 8 87
- VHDL Master BFM API 91
- April 2014 100
- Prototype 118
- Arguments 118
- VHDL Master BFM 122
- VHDL Slave BFM 123
- Chapter 9 123
- Slave BFM Configuration 124
- Slave Assertions 125
- VHDL Slave BFM API 126
- Chapter 10 157
- VHDL Monitor BFM 157
- Monitor BFM Configuration 158
- Monitor Assertions 159
- VHDL Monitor BFM API 161
- Chapter 11 181
- VHDL Tutorials 181
- Master BFM Test Program 182
- Verifying a Master DUT 185
- Chapter 12 189
- Running the Qsys Tool 193
- Running a Simulation 195
- ModelSim Simulation 196
- Editing the modelsim.ini File 199
- Questa Simulation 200
- Cadence IES Simulation 200
- Synopsys VCS Simulation 202
- Chapter 13 205
- Assertions 205
- Appendix A 209
- Programs 209
- Appendix B 213
- VHDL Slave BFM Code Example 216
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