Altera Hybrid Memory Cube Controller Manual do Utilizador descarregar pdf (Página 55)

XCVR_STATUS Register

Table 5-4: HMC Controller IP Core XCVR_STATUS Register at Offset 0x08

Individual transceiver status in HMC link, ordered by transceiver channel.

Bits Field Name Type Value on

Reset

Description

31:16 Reserved RO 0x0001

15:8 (half-

width IP

core)

Reserved RO 0x00

7:0 (half-

width IP

core)

CDR Lock RO 0x00

Each bit indicates whether the CDR for the

corresponding transceiver channel has locked to

the received data.

15:0 (full-

width IP

core)

CDR Lock RO 0x00

LANE_STATUS Register

Table 5-5: HMC Controller IP Core LANE_STATUS Register at Offset 0x0C

Individual lane status in HMC link, ordered by transceiver channel.

Bits Field Name Type Value on

Reset

Description

31:24

(half-

width IP

core)

Reserved RO 0x00

23:16

(half-

width IP

core)

WordLock RO 0x00

Each bit indicates whether the corresponding

transceiver channel in the HMC link has locked to

the TS1 word boundary.

31:16

(full-

width IP

core)

WordLock RO 0x0000

15:8

(half-

width IP

core)

Reserved RO 0x00

UG-01152

2015.05.04

XCVR_STATUS Register

5-3

HMC Controller IP Core Register Map

Altera Corporation

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1 2 ... 50 51 52 53 54 55 56 57 58 59 60 ... 68 69

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