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3–14 Chapter 3: Parameter Settings
Specify the Architecture Specification
FIR Compiler User Guide © May 2011 Altera Corporation
Coefficient Reload If you want to change coefficients, turn on this option. This option is available when you choose to
store coefficients in embedded memory.
Selecting this option increases resource usage, turns off several optimization schemes, and adds
additional input ports to the filter.
Pipeline Level Creates a higher performance filter with a resource usage increase.
Use Single Clock Use this option when creating designs with DSP Builder. This option is only available when
Coefficients Reload is selected and M512, M4K, MLAB or M9K is specified in Coefficient Storage.
This option ties the coef_clk_in and clk signals together.
Note to Table 3–6:
(1) The bit width of input data should divide evenly by the number of serial units and result of division must be greater than or equal to four.
Table 3–7. Fully Parallel Filter Architecture (Note 1)
Parameters Description
Data Storage Specifies the device resources used for data storage. You can select Logic Cells or Auto. If you
select Auto, the Quartus II software may store data in logic cells or memory, depending on the
resources in the selected device, the size of the data storage, and the number of input channels.
Coefficient Storage Specifies the device resources used for coefficient storage. You can select Logic Cells, M512,
M4K, MLAB, M9K, or Auto. If you select Auto, the Quartus II software automatically selects the
most appropriate memory block size for the selected device.
The option list changes depending on which device you select. Selecting embedded memory
reduces logic cell usage and may increase the speed of the filter.
Force Non-Symmetric
Structure
If you want to create a design that uses both symmetric and non-symmetric coefficients, turn on
this option. Non-symmetric architectures may use more resources.
This option is available when coefficients are stored in the embedded memory.
Coefficient Reload If you want to change coefficients, turn on this option. This option is available when you choose to
store coefficients in embedded memory.
Selecting this option increases resource usage, turns off several optimization schemes, and adds
additional input ports to the filter.
Pipeline Level Creates a higher performance filter with a resource usage increase.
Use Single Clock Use this option when creating designs with DSP Builder. This option is only available when
Coefficients Reload is selected and M512, M4K, MLAB or M9K is specified in Coefficient Storage.
This option ties the coef_clk_in and clk signals together.
Note to Figure 3–6:
(1) When input data is unsigned, the input data bit width should be greater than or equal to one. When input data is signed, the input data bit width
should be greater than or equal to two.
Table 3–6. Multibit Serial Filter Architecture (Part 2 of 2) (Note 1)
Parameters Description
- FIR Compiler 1
- User Guide 1
- UG-FIRCOMPILER 11.0 2
- Contents 3
- Additional Information 4
- 1. About the FIR Compiler 5
- Delay Line 6
- Coefficient 6
- Multipliers 6
- Adder Tree 6
- Features 7
- Release Information 8
- Device Family Support 9
- MegaCore Verification 10
- Notes to Table 1–5: 11
- Notes to Table 1–6: 11
- Installation and Licensing 12
- 2. Getting Started 15
- Figure 2–4. Set Up Simulation 18
- Notes to Table 2–1 21
- Simulate the Design 22
- Simulating in MATLAB 23
- 3. Parameter Settings 25
- Specifying the Coefficients 26
- Note to Figure 3–6: 31
- Analyzing the Coefficients 32
- Bits Removed from MSB 34
- Bits Removed from LSB 34
- Note to Table 3–4: 36
- Note to Table 3–5: 37
- Note to Table 3–6: 38
- Resource Estimates 40
- Filter Design Tips 40
- 4. Functional Description 43
- Coefficient Scaling 44
- Symmetrical Serial 45
- Structure Types 48
- Serial Structures 49
- Multibit Serial Structure 49
- Interpolation and Decimation 50
- Figure 4–8. Signal Decimation 51
- Pipelining 54
- Simulation Output 55
- Avalon Streaming Interface 55
- Data Source Data Sink 56
- Packet Data Transfers 57
- ■ 00: No error 58
- ■ 01: Missing SOP 58
- ■ 10: Missing EOP 58
- ■ 11: Unexpected EOP 58
- Timing Diagrams 59
- Referenced Documents 68
- Structures 69
- Supported Device Structures 70
- Compiling HardCopy Designs 71
- How to Contact Altera 74
- Typographic Conventions 74
- Additional Information Info–3 75
- Info–4 Additional Information 76
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