Altera Cyclone V GX FPGA Development Board Manual do Utilizador descarregar pdf (Página 47)

Chapter 2: Board Components 2–39

Memory

May 2013 Altera Corporation Cyclone V GX FPGA Development Board

Reference Manual

DDR3B_DQ9

D28 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ10

A29 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ11

H25 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ12

H24 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ13

H26 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ14

B28 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQ15

D27 1.5-V SSTL Class I Data bus byte lane 1

DDR3B_DQS_P0

N21

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 0

DDR3B_DQS_N0

M22

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 0

DDR3B_DQS_P1

P20

Differential 1.5-V SSTL

Class I

Data strobe P byte lane 1

DDR3B_DQS_N1

N20

Differential 1.5-V SSTL

Class I

Data strobe N byte lane 1

DDR3B_ODT

V29 1.5-V SSTL Class I On-die termination enable

DDR3B_RASN

T29 1.5-V SSTL Class I Row address select

DDR3B_RESETN

AB27 1.5-V SSTL Class I Reset

DDR3B_WEN

T28 1.5-V SSTL Class I Write enable

DDR3B_ZQ01

— 1.5-V SSTL Class I ZQ impedance calibration

DDR3 x16 (U15)

DDR3B_A0

Y30 1.5-V SSTL Class I Address bus

DDR3B_A1

R28 1.5-V SSTL Class I Address bus

DDR3B_A2

AA29 1.5-V SSTL Class I Address bus

DDR3B_A3

W29 1.5-V SSTL Class I Address bus

DDR3B_A4

U23 1.5-V SSTL Class I Address bus

DDR3B_A5

AA30 1.5-V SSTL Class I Address bus

DDR3B_A6

R23 1.5-V SSTL Class I Address bus

DDR3B_A7

AC30 1.5-V SSTL Class I Address bus

DDR3B_A8

T23 1.5-V SSTL Class I Address bus

DDR3B_A9

AB29 1.5-V SSTL Class I Address bus

DDR3B_A10

R30 1.5-V SSTL Class I Address bus

DDR3B_A11

R26 1.5-V SSTL Class I Address bus

DDR3B_A12

T25 1.5-V SSTL Class I Address bus

DDR3B_A13

AD29 1.5-V SSTL Class I Address bus

DDR3B_BA0

W30 1.5-V SSTL Class I Bank address bus

DDR3B_BA1

T24 1.5-V SSTL Class I Bank address bus

DDR3B_BA2

V30 1.5-V SSTL Class I Bank address bus

DDR3B_CASN

T30 1.5-V SSTL Class I Row address select

Table 2–30. DDR3B Device Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4)

Board Reference

Schematic

Signal Name

Cyclone V GX

Pin Number

I/O Standard Description

1 2 ... 42 43 44 45 46 47 48 49 50 51 52 ... 59 60

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