Altera Arria V GX FPGA Manual do Utilizador descarregar pdf (Página 38)

6–16 Chapter 6: Board Test System

Using the Board Test System

Arria V GX FPGA Development Kit July 2012 Altera Corporation

User Guide

The HSMB/FMC Tab

The HSMB tab (Figure 6–7) allows you to perform loopback tests on the XCVR and

CMOS ports.

1 You must have the loopback HSMB installed on the HSMC Port B connector that you

are testing for this test to work correctly.

The following sections describe the controls on the HSMB/FMC tab.

Status

The Status control displays the following status information during the loopback test:

■ PLL lock—Shows the PLL locked or unlocked state.

■ Channel lock—Shows the channel locked or unlocked state. When locked, all

lanes are word aligned and channel bonded.

■ Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

Figure 6–7. The HSMB/FMC Tab

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Altera Arria V GX FPGA Manual do Utilizador Página 38