Altera ALTDLL Manual do Utilizador descarregar pdf (Página 59)

4–23 Chapter 4: Functional Description

DQS_CONFIG / IO_CONFIG Block

ALTDLL and ALTDQ_DQS Megafunctions User Guide © February 2012 Altera Corporation

In all cases, the most significant bit (MSB) of the delay chain values is shifted in first

and the least significant bit (LSB) is shifted in last. For example, in the first four

configuration clock cycles, the first configuration clock cycle corresponds to the MSB

of the input delay chain value and the fourth configuration clock cycle corresponds to

the LSB.

The delay only takes effect when the config_update signal is asserted for one

configuration clock cycle, in which all the bits in the serial shift register feeds an

11–bit, parallel-loaded register. Right after the signal is deasserted, you can observe

the delay from datain (of the delay chain primitive) to dataout (of the delay chain

block).

For all delay chains, each delay setting increment adds approximately 50 ps of delay

(the actual value depends on the device speed grade); therefore, the total delay value

is equal to the number of stages in the delay chain ×50 ps. For example, if you set the

number of stages in the delay chain to five, then the total delay value is five times

50 ps, which is 250 ps.

Figure 4–19 through Figure 4–23 are simulation examples that show the results of

varying the delay at the input delay chain (D1).

f For more information about controlling these delay chains and how to vary the

output delay chains (D5 and D6), refer to the Design Example 1: Dynamically Changing

Delay Chains in Output Buffer of Stratix III section of the I/O Buffer ALTIOBUF

Megafunction User Guide.

Setting the Input Delay Chain (D1) to Zero Delay (default)

Figure 4–19 shows that there are no timing difference with the cursor at 70 ns when

D1 is set to zero delay. The cursor at 70 ns represents the path from the bidirectional

buffer (bidir_dq_input_data_in) through the input delay chain

(bidir_dq_0_input_delay_chain_inst). You can view the effects of the delay

chain by comparing the datain port and the dataout port of the

bidir_dq_0_input_delay_chain_inst.

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 116 117

Sem comentários

Altera ALTDLL Manual do Utilizador Página 59