Altera 100G Development Kit, Stratix IV GT Edition Manual do Utilizador Página 53

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Chapter 2: Board Components 2–45
Components and Interfaces
September 2010 Altera Corporation 100G Development Kit, Stratix IV GT Edition Reference Manual
Table 232 lists the CFP interface component reference and manufacturing
information.
Interlaken Interface
The Interlaken interface consists of 20 full-duplex transceiver channels with
AC-coupling on the receiver data.
Table 235 lists the pin assignments for the Interlaken interface and their
corresponding schematic signal names and Stratix IV GT pin numbers.
Table 2–34. CFP interface Component Reference And Manufacturing Information
Board
Reference
Description Manufacturer
Manufacturing
Part Number
Manufacturer
Website
J37 CFP host board receptacle connector AMP/Tyco 2057630-1 www.samtec.com
Table 2–35. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 4)
Board
Reference
Description
Schematic
Signal Name
i/O
Standard
Stratix IV GT
Device
Pin Name
Other
Connections
J57.A7 Transmit XCVR pair 0 from FPGA
INT_TX_P0
1.2-V
PCML
AG41
J57.B7 Transmit XCVR pair 0 from FPGA
INT_TX_N0
AG42
J57.D6 Transmit XCVR pair 1 from FPGA
INT_TX_P1
AL41
J57.E6 Transmit XCVR pair 1 from FPGA
INT_TX_N1
AL42
J57.D8 Transmit XCVR pair 2 from FPGA
INT_TX_P2
AE41
J57.E8 Transmit XCVR pair 2 from FPGA
INT_TX_N2
AE42
J57.A9 Transmit XCVR pair 3 from FPGA
INT_TX_P3
AC41
J57.B9 Transmit XCVR pair 3 from FPGA
INT_TX_N3
AC42
J57.A3 Transmit XCVR pair 4 from FPGA
INT_TX_P4
AW41
J57.B3 Transmit XCVR pair 4 from FPGA
INT_TX_N4
AW42
J57.D2 Transmit XCVR pair 5 from FPGA
INT_TX_P5
BA38
J57.E2 Transmit XCVR pair 5 from FPGA
INT_TX_N5
BB38
J57.D4 Transmit XCVR pair 6 from FPGA
INT_TX_P6
AU41
J57.E4 Transmit XCVR pair 6 from FPGA
INT_TX_N6
AU42
J57.A5 Transmit XCVR pair 7 from FPGA
INT_TX_P7
AN41
J57.B5 Transmit XCVR pair 7 from FPGA
INT_TX_N7
AN42
J57.G5 Transmit XCVR pair 8 from FPGA
INT_TX_P8
AR41
J57.H5 Transmit XCVR pair 8 from FPGA
INT_TX_N8
AR42
J57.G3 Transmit XCVR pair 9 from FPGA
INT_TX_P9
BA40
J57.H3 Transmit XCVR pair 9 from FPGA
INT_TX_N9
BB40
J30.A7 Transmit XCVR pair 10 from FPGA
INT_TX_P10
B42
J30.B7 Transmit XCVR pair 10 from FPGA
INT_TX_N10
A42
J30.D6 Transmit XCVR pair 11 from FPGA
INT_TX_P11
G41
J30.E6 Transmit XCVR pair 11 from FPGA
INT_TX_N11
G42
J30.D8 Transmit XCVR pair 12 from FPGA
INT_TX_P12
D39
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